Logic Gates

The 74HC00 contains four NAND gates^[1]. This page wires three of them into three different logical functions, verifies each against its truth table, and ends with the NOT gate that will appear again as the ROM chip-enable inverter in f03b.

The 74HC00

Seat the 74HC00 on the breadboard. The chip is a DIP-14: 14 pins, notch on one end marking pin 1. Pin 14 is VCC (connect to +5V). Pin 7 is GND (connect to the ground rail). Add a 100nF decoupling capacitor between VCC and GND, physically close to the chip.

The four gates share the power and ground pins. Each gate has two input pins and one output pin:

The NAND gate

The NAND gate's output is LOW only when both inputs are HIGH. In all other combinations the output is HIGH.

Wire gate 1 (pins 1, 2, 3). Connect pin 1 to a free wire (input A). Connect pin 2 to a second free wire (input B). Connect pin 3 through a 1kΩ resistor to the anode of a LED; connect the LED cathode to GND.

To show the current input state, add indicator LEDs: connect a 1kΩ resistor and LED from each input wire to GND. When the input is HIGH the indicator LED lights; when LOW it is off.

Work through each row of the truth table by setting each input wire to +5V (HIGH) or GND (LOW). The output LED should match the Output column.

The only row where the output LED turns off is the last row: both inputs HIGH simultaneously.

The NOT gate (inverter)

A NOT gate^[2] has one input and one output. The output is the logical inverse of the input: HIGH in → LOW out, LOW in → HIGH out.

Build a NOT gate by tying both inputs of a NAND gate together. When both inputs receive the same signal:

• Signal LOW → both inputs LOW → NAND output HIGH (row 1 of the NAND table)
• Signal HIGH → both inputs HIGH → NAND output LOW (row 4 of the NAND table)

The two middle rows never occur because both inputs are always identical. The result is a NOT: output = NOT(input).

Wire gate 2 (pins 4, 5, 6). Connect pin 4 and pin 5 together with a short jumper, then connect both to a single input wire. Connect pin 6 through a 1kΩ resistor and LED to GND.

Set the input to LOW: output LED lights. Set the input to HIGH: output LED turns off. The output is always the opposite of the input.

This is the circuit in f03b. ROM CE# connects to pin 6. CPU A15 connects to pins 4 and 5. When A15 is HIGH ($8000–$FFFF, ROM space) the output is LOW — CE# active, ROM selected. When A15 is LOW ($0000–$7FFF, RAM space) the output is HIGH — CE# inactive, ROM deselected. One gate, the complete ROM address decode.

The AND gate

An AND gate's output is HIGH only when both inputs are HIGH. In all other combinations the output is LOW — the inverse of a NAND.

Build an AND gate by connecting a NAND output directly into a NOT input. The NAND output is LOW only when both inputs are HIGH; the NOT inverts that LOW to a HIGH. Every other combination produces a NAND output of HIGH, which the NOT inverts to LOW.

Wire gate 3 as a NAND (pins 8, 9, 10) with two input wires and the output going to pin 11 of gate 4. Tie pins 11 and 12 together. Connect pin 13 through a 1kΩ resistor and LED to GND.

The final LED (gate 4 output) is now the AND of the two input wires. Both inputs LOW: final output LOW. Either input LOW: final output LOW. Both inputs HIGH: final output HIGH — the only combination where the LED lights.

Work through all four input combinations and verify the table.

What the chip contains

Three gate configurations from one 14-pin chip, using three of the four available gates. The 74HC00 in f03b uses one gate — the NOT on A15. The other three gates are available for future decode logic as the memory map becomes more complex.

Every address decoder in every computer is a variation of what you just built: combinations of NAND and NOT gates that turn address lines into chip-enable signals. The 74LS00 in the Asteroids arcade cabinet does the same work at a million times the speed. The logic is identical.