The first stage is getting stable power and a running clock into the 6502. No ROM yet, no RAM — just the CPU with all its control inputs tied to safe states, a reset circuit, and the oscillator module feeding PHI2 (Φ2) — the clock input pin that drives every internal operation of the 6502. Without a signal on PHI2, the CPU is completely inert; it is the heartbeat of the chip.
The CPU will not execute anything meaningful because there is no program to fetch, but by the end of this page you will have confirmed that power is clean and the chip is alive.
Breadboard layout
Use three half-size breadboards placed end to end. The W65C02S[1] is a DIP-40 package — 20 pins per side — and it spans most of one board on its own. Place the CPU centred on the first board, straddling the middle channel so each row of pins has its own set of tie points. Leave the second board empty for now; it will carry the ROM and RAM. Use the third for the decode logic, the address LEDs, and anything else that does not fit near the CPU.
Run the power rails before placing any chip. Connect the top red rail to +5V and the top blue rail to GND across all three boards. Bridge the bottom rails to match. A breadboard's power rails do not run the full length on some models — check with a multimeter before assuming a continuous connection.
Seating the 6502
The W65C02S is a DIP-40. Orient pin 1 toward the top-left — the notch or dot on the chip body marks pin 1. Press it down firmly and evenly. If it is seated at an angle, the row of pins on the short side will bridge across two rows of tie points instead of one, and you will spend an hour wondering why nothing works.
Once it is seated, verify by counting: pin 1 top-left, pin 20 bottom-left, pin 21 bottom-right, pin 40 top-right. Each pin should sit in its own tie point with no bridging.
Power rail
Connect CPU pin 8 (VCC) to the +5V rail and CPU pin 21 (GND) to the GND rail with short jumper wires.
Immediately beside the CPU, place a 100nF ceramic capacitor between the VCC and GND rails — as physically close to pin 8 as possible. This is a decoupling capacitor. Every time a gate inside the CPU switches state, it draws a brief pulse of current from the supply. Without the capacitor, that pulse causes a small voltage dip on the rail, which can propagate along the breadboard wires and corrupt the logic level seen by other pins. The 100nF cap acts as a local charge reservoir: it supplies the pulse from its own stored charge before the supply has time to respond, keeping the rail stable. Add one of these next to every IC in the circuit.
Tie-off pins
Several 6502 control inputs must be held at a defined logic level. Floating inputs are undefined — the pin can drift between 0 and 1 depending on stray capacitance and noise, and the CPU will behave unpredictably.
Connect the following to +5V through 10kΩ pull-up resistors:
- Pin 4 (IRQB — interrupt request, active low). Pulling it high disables interrupts.
- Pin 6 (NMIB — non-maskable interrupt, active low). Pulling it high disables the NMI.
Connect the following directly to +5V (no resistor needed; these are not shared with any other driver):
- Pin 2 (RDY — ready). High means "run normally". Pulling it low would pause the CPU between cycles; we do not want that.
- Pin 38 (SOB — set overflow). Active low; tie high to disable.
- Pin 36 (BE — bus enable). High enables the address and data bus drivers. Pulling it low would tri-state all bus outputs; the CPU would go silent on the bus.
Leave pins 9–25, 26–33, and 34 (address bus, data bus, and RWB) unconnected for now. They will be wired when the ROM and RAM are added. Floating address and data pins are fine at this stage because the CPU has nowhere to drive them to and nothing else is listening.
Reset circuit
The 6502 starts executing after a proper reset sequence: RESB (pin 40) must be held low for at least two clock cycles, then rise to high. When RESB rises, the CPU reads the 16-bit reset vector from addresses FFFD and jumps there.
Wire the reset circuit as follows. Place a 10kΩ resistor between pin 40 (RESB) and the +5V rail. Then place a 10µF electrolytic capacitor between pin 40 and GND, with the positive leg at pin 40. The polarity of the capacitor matters — the positive leg is marked with a longer lead and the negative leg is marked with a stripe on the body.
On power-up, the capacitor is uncharged and holds pin 40 close to 0V. Current flows through the resistor into the capacitor; the voltage at pin 40 rises with the RC time constant. With 10kΩ and 10µF, the time constant is 100ms. By the time the supply rails have settled and the oscillator module has locked, RESB has risen above the logic-high threshold and the CPU begins the reset sequence. If you skip this circuit and tie RESB directly to VCC, the CPU may start before the oscillator has stabilised, fetch garbage, and hang.
Clock circuit
The 1 MHz crystal oscillator module has four pins in a DIP-4 package. The pinout varies slightly by manufacturer, so check the datasheet before wiring, but the most common arrangement is:
- Pin 1: no connect (NC)
- Pin 7: GND
- Pin 8: output (OUT)
- Pin 14: VCC
Seat the oscillator module on the breadboard near the CPU. Connect its VCC pin to the +5V rail, its GND pin to GND, and its OUT pin to CPU pin 37 (PHI2 — phase 2 clock input).
PHI2 is the primary clock input for the W65C02S. On the rising edge of PHI2 the CPU advances its internal state machine. At 1 MHz, that is one million rising edges per second — one clock cycle every microsecond. Add a 100nF decoupling capacitor next to the oscillator module just as you did for the CPU.
Verification
Before going any further, confirm the power connections are correct. Apply power and measure the following with your multimeter set to DC voltage:
- CPU pin 8 (VCC) to GND: should read +5V ± 0.25V.
- CPU pin 21 (GND) to GND: should read 0V.
If the voltage is wrong, remove power immediately and check your wiring before touching anything else. A reversed polarity or a short between VCC and GND will damage the CPU.
If the voltage is correct, check that the oscillator module is running. A logic probe will show a pulsing signal on PHI2 (pin 37). A multimeter in AC voltage mode will show approximately 2.5V RMS on that pin if the clock is running, though this is not a reliable measurement at 1 MHz — a logic probe or oscilloscope is better. If you have neither, proceed: the oscillator module either works or it does not, and the circuit will show the difference when the ROM is added.
The CPU is not executing anything yet. There is no ROM to provide instructions, and the data bus is floating. That is fine. This page established stable power and a running clock — the prerequisite for everything that follows.